• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    This invention relates to message switching by means of memory array 1. The purpose of the shadow inventive is to improve performance. The device contains a memory matrix, a synchronization block, source and receiver address counters, a write-read block, a clock counter, a transceiver block, and a block for specifying initial conditions. The device is invalidated by the fact that each row of the matrix contains a group of elements of the associative memory of the source and receiver, a group of elements of the RAM, and two matching blocks 2 or more. with S (L
    公开号:SU1447296A3
    申请号:SU853983649
    申请日:1985-12-12
    公开日:1988-12-23
    发明作者:Рональд Юдичак Джозеф；Джозеф Тогель Герберт
    申请人:Интернэшнл Стандарт Электрик Корпорейшн (Фирма)；
    IPC主号:
    专利说明:

    The invention relates to a device for establishing switching circuits and, more precisely, to a device with the aid of which dynamically assigned chains to information sources and information receivers.
    The aim of the invention is to increase productivity.
    Figure 1 and 2 presents the scheme of the device.
    The device contains a matrix of 1 memory elements containing the corpse of elements 2 of the associative memory of the source address, a group of elements 3 of the operative memory, a group of elements 4 of the associative memory of the receiver's address that have many words that must be sufficient to form all the necessary chains switching system.
    In addition, the device contains a synchronization unit 2, a write / read unit 6, a counter 7 (reversible) source ad, a counter 8 (reversible) of a receiver address, a 9 clock counter, a block 10 of transceivers, a set 11 initial conditions, blocks 12 and 13 harmonization, elements 14 and 15 of one-sided conductance, address; source bus 16, comparison linsho 17, line — 18 lines of a word, data bus 19, address receiver bus 20, comparison bus 21.
    The operation of the device is described under the condition that the number of the source and destination addresses has already been entered into elements 2 and 4 of the memory of the source address and the Information Receiver, respectively, using LOCK 10. When the address arrives on the address bus 16 of the information source from counter 7, all elements 2 of the memory of the information source will produce a comparison function. If each bit for the memorized word address coincides with each bit on the address bus 16 of the information source, then a logical level 1 will be provided on the comparison line 7. If any of the compared bits does not match, its adrenal memory element will pull out the level Logical, general-purpose drive) line 17 comparison to the level of logging tjecKoro O.
    The comparison line I7 is connected to line 18 of the word of the memory elements with an arbitrary; sample through
    with
    about
    50
    50
    eg 0 5 g 5
    element 14. Thus, if each bit of the address bus of the source of information coincides with the address of the memorized word in elements 2, then the logical level 1 to the line 18 of the word will be output, thereby preparing for operation each of the 3 memory elements during the interval time following the strobing of counter 7 using counter 9. During this subsequent period of time, counter 9 gates the transceiver unit 10 corresponding to the address gated from counter 7, which causes the transceiver to transmit The data contained therein is on the data bus 19, so that the parallel bits of the data can be written to the memory elements 3.
    Similarly, counter 9 gates the receiver address counter 8 for an appropriate period of time just prior to building the transceiver of the receiver's addressed channel 10, so that the bits of the address of the receiver of information are fed to the discharge buses of the memory elements 4 of the receiver's address. If the address represented on the address bus 20 of the information receiver is stored in the memory elements 4 of the receiver, then each oazp will be compared and the output with a logic level will be provided to the comparison bus 21, which will output the logic level I to. the element 15, thus creating the possibility for the operation of the elements 3 of the memory of the addressed word. The data contained in the ready-to-work memory elements 3 can be read and placed on multiplexed data transmission devices with time division TDM for communication with the gated transceiver unit 10 according to the address received from the address bus 20 of the information receiver.
    It is possible to have the source address and not have the receiver's address, while the information will be stored for later use. In basic cases, permanent data can be stored in a word with data that is read at the destination address of the information, while the word does not have the source address.
    During the setup mode, a new word is recorded by recording the address of the source of information, the address of the receiver of information and data. Additional commands that may occur during setup mode contain word cancellation and use the address memory or source, or
    receiver addresses, the counting inputs of which and the synchronous inputs of the transceiver unit and the synchronization unit are connected to the output of the clock counter, whose input is the synchronous input device, the second group of information inputs and outputs of the transceiver unit are informational
    the recipient of the information as the address of the 10 inputs / outputs of the device, the group of reading or writing another part of the address memory and / or data memory with a random selection.
    The invention may in its most general form provide a set of pre-appointed. switching circuits, as well as their dynamic establishment, in which the switching circuits can be assigned and canceled using commands. Moreover, it can establish switching circuits between special ports and time-separated channels of these ports. In this way.
    synchronization block moves are connected to a group of synchronous inputs of the initial conditions set block, the first and second address inputs of which are connected respectively to information inputs, reversible address counters and receiver addresses, characterized in that, in order to improve performance, each row of the matrix of memory elements contains a group of elements associative memory of the source address, a group of elements of the associative memory of the address of the receiver, two matching blocks and a group; data RAM.
    extremely flexible switching for both spatial and temporal switching.
    权利要求:
    Claims (1)
    [1]
    Claim 30
    40
    A device for exchanging data containing a matrix of memory elements, a synchronization unit, a write-read unit, a source address counter, counting. The receiver's address, clock counter, transceiver unit and initial conditions setting unit, the first group of information inputs and outputs of the transceiver unit are connected to the first group of information inputs and outputs of the read / write unit, the first and second outputs of the synchronization unit are connected respectively to the synchronous inputs of the counters source addresses and
    input-output device, the group of
    synchronization block moves are connected to a group of synchronous inputs of the initial conditions set block, the first and second address inputs of which are connected respectively to information inputs, reversible address counters and receiver addresses, characterized in that, in order to improve performance, each row of the matrix of memory elements contains a group of associative memory of the source address, a group of elements of the associative memory of the receiver's address, two matching blocks and a group of ele
    the setting inputs and the reset inputs of the associative memory of the source address of the group are connected to the outputs of the source address counter via the first matching block; the reset of the elements of the operating memory of the data group are connected to the outputs of the write-read block; in each row of the matrix, output 0 of the elements of the associative memory of the address is used regular enrollment and addresses of groups of receiver elements are connected via a one-way conduction element with the enable input of operational data memory groups.
    five
    81 01. 8i BL
    Jl
    L
    n
    iiin PE
    I
    T111Sh11SHI11
    类似技术:
    公开号 | 公开日 | 专利标题
    SU1447296A3|1988-12-23|Swapping device
    US4771420A|1988-09-13|Time slot interchange digital switched matrix
    US5031094A|1991-07-09|Switch controller
    US3678205A|1972-07-18|Modular switching network
    US4935922A|1990-06-19|Packet data switch for transferring data packets from one or a plurality of incoming data links to one or a plurality of outgoing data links
    US4488290A|1984-12-11|Distributed digital exchange with improved switching system and input processor
    GB1288195A|1972-09-06|
    KR950025840A|1995-09-18|Multi-Bank Synchronous Memory System with Cascaded Memory Cell Structure
    JPH03182140A|1991-08-08|Common buffer type exchange
    ES8305516A1|1983-04-01|Computer system.
    EP0121726A3|1985-01-09|Multi-port memory cell and system
    EP0025225A1|1981-03-18|Broadcast and alternate message time slot interchanger
    CA2008669A1|1990-11-05|Multiple mode memory module
    JPH02123589A|1990-05-11|Memory system
    SU650526A3|1979-02-28|Multiplexing device
    GB1296181A|1972-11-15|
    KR930003592A|1993-02-24|Time slot designator and time slot method for use in a series of communication systems
    KR910010530A|1991-06-29|High speed recording circuit in RAM test
    US6363017B2|2002-03-26|Method and apparatus for alternate operation of a random access memory in single-memory operating mode and in combined multi-memory operating mode
    GB2097623A|1982-11-03|Memory
    US4833674A|1989-05-23|Arrangement for processing received data in TDMA communications system and method therefor a TDMA communications system and method for retrieving received data in a preset order
    US4564938A|1986-01-14|Digital electronic switching systems
    US3999162A|1976-12-21|Time-division multiplex switching circuitry
    US4218588A|1980-08-19|Digital signal switching system
    GB1465076A|1977-02-23|Pcm tdm telecommunications systems
    同族专利:
    公开号 | 公开日
    MA20587A1|1986-07-01|
    AU5104285A|1986-06-19|
    EP0184774A2|1986-06-18|
    FI854947A|1986-06-15|
    HUT41932A|1987-05-28|
    PT81644B|1987-01-07|
    CN85108417A|1986-07-16|
    ES549926A0|1987-11-16|
    FI854947A0|1985-12-13|
    ES8800814A1|1987-11-16|
    BE903855R|1986-06-16|
    PT81644A|1986-01-02|
    JPS61144194A|1986-07-01|
    PH22019A|1988-05-13|
    YU194585A|1988-08-31|
    US4656626A|1987-04-07|
    NO855050L|1986-06-16|
    ZA858750B|1986-07-30|
    EP0184774A3|1988-09-21|
    BR8506025A|1986-08-19|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    CH517419A|1970-12-24|1971-12-31|Ibm|Time division multiplex switch|
    DE2308866C2|1973-02-22|1974-12-12|Siemens Ag, 1000 Berlin Und 8000 Muenchen|Circuit arrangement for the detection of double connections in time-division multiplex digital telecommunications switching systems, in particular PCM telephone switching systems|
    NL7313573A|1973-10-03|1975-04-07|Philips Nv|MEMORY DEVICE.|
    JPS5712222B2|1977-12-27|1982-03-09|
    JPS54128634A|1978-03-30|1979-10-05|Toshiba Corp|Cash memory control system|
    US4168541A|1978-09-25|1979-09-18|Sperry Rand Corporation|Paired least recently used block replacement system|
    FR2440672B1|1978-10-30|1981-05-08|Cit Alcatel|
    FR2454242B1|1978-12-26|1986-02-14|Servel Michel|TIME DIVISION MULTIPLEX SWITCHING NETWORK IN WHICH THE BUFFER MEMORY IS ASSOCIATIVE, CIRCULATED AND IN THE FORM OF A COUPLED LOAD DEVICE|
    DE2934379A1|1979-08-24|1981-03-26|Siemens AG, 1000 Berlin und 8000 München|MULTIPLE TIMES FOR A TIME MULTIPLEX SYSTEM FOR THE COUPLING OF DIGITAL, IN PARTICULAR DELTA MODULATED, MESSAGE SIGNALS|
    US4382295A|1981-04-23|1983-05-03|Bell Telephone Laboratories, Incorporated|Digital conference time slot interchanger|
    DE3122300A1|1981-06-04|1982-12-23|Siemens AG, 1000 Berlin und 8000 München|CIRCUIT ARRANGEMENT FOR TIME MULTIPLEX TELECOMMUNICATION PLANTS, ESPECIALLY PCM TELEPHONE PABX, WITH TIME MULTIPLEX CABLES, THEIR TIME CHANNELS PART FOR MESSAGE CONNECTIONS AND PARTIAL INFORMATION FOR NOTIFICATION INFORMATION|
    JPH024192B2|1983-08-05|1990-01-26|Nippon Telegraph & Telephone|US4972338A|1985-06-13|1990-11-20|Intel Corporation|Memory management for microprocessor system|
    US5173872A|1985-06-13|1992-12-22|Intel Corporation|Content addressable memory for microprocessor system|
    DE3535215C2|1985-10-02|1989-10-26|Nixdorf Computer Ag, 4790 Paderborn, De|
    JPH0375899B2|1985-11-19|1991-12-03|Matsushita Electric Ind Co Ltd|
    US4758982A|1986-01-08|1988-07-19|Advanced Micro Devices, Inc.|Quasi content addressable memory|
    US4858180A|1986-02-28|1989-08-15|Data General Corporation|Content addressable memory and self-blocking driver|
    US4748618A|1986-05-21|1988-05-31|Bell Communications Research, Inc.|Telecommunications interface|
    US5226147A|1987-11-06|1993-07-06|Mitsubishi Denki Kabushiki Kaisha|Semiconductor memory device for simple cache system|
    US4862412A|1988-04-25|1989-08-29|Gte Laboratories Incorporated|Content-addressable memory having control circuitry and independent controls for match and write cycles|
    US4918329B1|1988-07-25|1993-06-01|Data transmission system|
    IT1230235B|1989-06-07|1991-10-18|Telettra Spa|STRUCTURING AND PACKAGE TRANSMISSION OF THE INFORMATION GENERATED BY CODER FOR VIDEO SIGNALS.|
    FR2669496B1|1990-11-21|1995-03-31|Alcatel Business Systems|TIME SWITCH WITH EXPLODED ARCHITECTURE AND CONNECTION MODULE FOR THE ESTABLISHMENT OF SUCH A SWITCH.|
    US5311462A|1991-12-19|1994-05-10|Intel Corporation|Physical placement of content addressable memories|
    US5574274A|1995-02-21|1996-11-12|Microtek International, Inc.|Transmissive/reflective optical scanning apparatus|
    US5862135A|1996-10-10|1999-01-19|Lucent Technologies Inc.|Simplified interface to a time-division multiplexed communications medium|
    US6199140B1|1997-10-30|2001-03-06|Netlogic Microsystems, Inc.|Multiport content addressable memory device and timing signals|
    US6148364A|1997-12-30|2000-11-14|Netlogic Microsystems, Inc.|Method and apparatus for cascading content addressable memory devices|
    US6219748B1|1998-05-11|2001-04-17|Netlogic Microsystems, Inc.|Method and apparatus for implementing a learn instruction in a content addressable memory device|
    US6240485B1|1998-05-11|2001-05-29|Netlogic Microsystems, Inc.|Method and apparatus for implementing a learn instruction in a depth cascaded content addressable memory system|
    US6381673B1|1998-07-06|2002-04-30|Netlogic Microsystems, Inc.|Method and apparatus for performing a read next highest priority match instruction in a content addressable memory device|
    US6570887B2|1999-01-22|2003-05-27|Intel Corporation|Method and apparatus employing associative memories to implement message passing|
    US6597690B1|1999-01-22|2003-07-22|Intel Corporation|Method and apparatus employing associative memories to implement limited switching|
    US6499081B1|1999-02-23|2002-12-24|Netlogic Microsystems, Inc.|Method and apparatus for determining a longest prefix match in a segmented content addressable memory device|
    US6460112B1|1999-02-23|2002-10-01|Netlogic Microsystems, Llc|Method and apparatus for determining a longest prefix match in a content addressable memory device|
    US6574702B2|1999-02-23|2003-06-03|Netlogic Microsystems, Inc.|Method and apparatus for determining an exact match in a content addressable memory device|
    US6892272B1|1999-02-23|2005-05-10|Netlogic Microsystems, Inc.|Method and apparatus for determining a longest prefix match in a content addressable memory device|
    US6539455B1|1999-02-23|2003-03-25|Netlogic Microsystems, Inc.|Method and apparatus for determining an exact match in a ternary content addressable memory device|
    US6137707A|1999-03-26|2000-10-24|Netlogic Microsystems|Method and apparatus for simultaneously performing a plurality of compare operations in content addressable memory device|
    US6934795B2|1999-09-23|2005-08-23|Netlogic Microsystems, Inc.|Content addressable memory with programmable word width and programmable priority|
    US7272027B2|1999-09-23|2007-09-18|Netlogic Microsystems, Inc.|Priority circuit for content addressable memory|
    US7143231B1|1999-09-23|2006-11-28|Netlogic Microsystems, Inc.|Method and apparatus for performing packet classification for policy-based packet routing|
    US7487200B1|1999-09-23|2009-02-03|Netlogic Microsystems, Inc.|Method and apparatus for performing priority encoding in a segmented classification system|
    US6944709B2|1999-09-23|2005-09-13|Netlogic Microsystems, Inc.|Content addressable memory with block-programmable mask write mode, word width and priority|
    US6567340B1|1999-09-23|2003-05-20|Netlogic Microsystems, Inc.|Memory storage cell based array of counters|
    US7110407B1|1999-09-23|2006-09-19|Netlogic Microsystems, Inc.|Method and apparatus for performing priority encoding in a segmented classification system using enable signals|
    US6757779B1|1999-09-23|2004-06-29|Netlogic Microsystems, Inc.|Content addressable memory with selectable mask write mode|
    US6687785B1|2000-06-08|2004-02-03|Netlogic Microsystems, Inc.|Method and apparatus for re-assigning priority in a partitioned content addressable memory device|
    US6542391B2|2000-06-08|2003-04-01|Netlogic Microsystems, Inc.|Content addressable memory with configurable class-based storage partition|
    US6763425B1|2000-06-08|2004-07-13|Netlogic Microsystems, Inc.|Method and apparatus for address translation in a partitioned content addressable memory device|
    US6324087B1|2000-06-08|2001-11-27|Netlogic Microsystems, Inc.|Method and apparatus for partitioning a content addressable memory device|
    US6799243B1|2000-06-14|2004-09-28|Netlogic Microsystems, Inc.|Method and apparatus for detecting a match in an intra-row configurable cam system|
    US6795892B1|2000-06-14|2004-09-21|Netlogic Microsystems, Inc.|Method and apparatus for determining a match address in an intra-row configurable cam device|
    US6751701B1|2000-06-14|2004-06-15|Netlogic Microsystems, Inc.|Method and apparatus for detecting a multiple match in an intra-row configurable CAM system|
    US6438017B1|2001-01-09|2002-08-20|Hewlett-Packard Company|Read/write eight-slot CAM with interleaving|
    JP2003324464A|2002-04-30|2003-11-14|Fujitsu Ltd|Data search apparatus and data search method|
    US7116015B2|2003-01-23|2006-10-03|Dell Products L.P.|System and method for dynamically configuring an information handling system|
    US8327116B1|2003-12-08|2012-12-04|Alcatel Lucent|System and method for processing multiple types of data frames|
    US7240175B1|2003-12-08|2007-07-03|Alcatel|Scheduling data frames for processing: apparatus, system and method|
    US7848129B1|2008-11-20|2010-12-07|Netlogic Microsystems, Inc.|Dynamically partitioned CAM array|
    US7920399B1|2010-10-21|2011-04-05|Netlogic Microsystems, Inc.|Low power content addressable memory device having selectable cascaded array segments|
    US8467213B1|2011-03-22|2013-06-18|Netlogic Microsystems, Inc.|Power limiting in a content search system|
    KR101970712B1|2012-08-23|2019-04-22|삼성전자주식회사|Device and method for moving data in terminal|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US06/682,033|US4656626A|1984-12-14|1984-12-14|Apparatus and method for providing dynamically assigned switch paths|
    [返回顶部]